Control system having column timers at each end

ABSTRACT

A control system for disposing each of a plurality of utilization circuits in a state responsive to the state of corresponding utilization controls. A plurality of seriesconnected coders detect the state of the utilization controls associated therewith. Decoders associated with each of said coders and in series connection in the same sequence as said corresponding coders control the state of the corresponding utilization circuits. A column timer is connected to each end of the series connections of said coders and decoders for applying control signals thereto. Each of the coders and decoders is sequentially activated to a first active state, during which they are operative to perform their assigned functions. Thereafter, each activated coder and decoder assumes an inactive state in which they permit the passage of control signals and data therethrough. The control signals can be applied in either direction along said series connections from either of said column timers.

United States Patent [191 Reich 51 June 5, 1973 [54] CONTROL SYSTEMHAVING COLUMN [57] ABSTRACT TIMERS AT EACH END A control system fordisposing each of a plurality of [75] Inventor: Zygmuud Reich,Huntington, N.Y. utilization circuits in a state responsive to the stateof corresponding utilization controls. A plurality of se- [73] Asslgnee'gfiz gg fi g f Corponmon ties-connected coders detect the state of theutilization controls associated therewith. Decoders as- Filed: P 24,1972 sociated with each of said coders and in series connec- [21] AWLNo; 246,919 tion in the same sequence as said corresponding coderscontrol the state of the corresponding utilization circuits. A columntimer is connected to each end [52] US. Cl. ..340/l63 R, 340/ 147 R fthe series connections f Said coders and decoders [51] Int. Cl. ..H04g9/00 for applying control signals net-eta h of the [58] Field of Search..340/ 163 R, 147 R coders and decoders is sequentially activated to afirst active state, during which they are operative to per- [56]References and form their assigned functions. Thereafter, each ac- UNTEDSTATES PATENTS tivated coder and decoder assumes an inactive state inwhich they permit the passage of control signals and 3,585,595 6/1971Slavin ..340/l63 R Primary Exa minerHarold I. Pitts Attorney-AlexFriedman, Harold I. Kaplan, and James K. Silberman data therethrough.The control signals can be applied in either direction along said seriesconnections from either of said column timers.

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I u I l l28| 1 I 4 L/ I l C T 5 z .A r4 x4 1 I I m Patented June 5, 19734 Sheets-Sheet 1 4 Sheets-Sheet 5 mmmy Rwy

Patented June 5, 1973 wwN wwwuww mi 4 Sheets-Sheet 4 WM a Qbk vbKmvCONTROL SYSTEM HAVING COLUMN TIMERS AT EACH END BACKGROUND OF THEINVENTION This invention relates generally to control systems utilizedto permit the control from a plurality of discrete stations of aplurality of utilization circuits associated therewith. An example ofsuch a system would be the service system of an aircraft, wherein theplurality of stations are the seat locations therein. Another example ofsuch a system would be a burglar and/or fire alarm system, wherein theplurality of stations are the monitoring stations therein. Each seat orgroup of seats has a number of utilization circuits associated there-'with, such as service call lights and lamps for reading or generalillumination which are to be controlled from the seats. In addition,each seat or group of seats has one or more automatically operatedsystems associated therewith, such as the oxygen systems. In the art, itwas customary to provide direct wiring between a utilization control,such as a switch at each seat, and the corresponding utilizationcircuit. However, this approach resulted in large amounts of cabling andtherefore added expense and weight in the aircraft. Still furthercabling and expense was added to the cost of the system if centrallylocated supervisory utilization circuits,

such as a central attendant call light responsive to the remotelylocated supervisory control means, were provided.

As an alternative to direct wiring between the individual utilizationcontrols and corresponding utilization circuits, systems utilizingmultiplexing techniques have been proposed. One such system is disclosedin U.S. Pat. No. 3,566,038, issued on Feb. 23, 1971, to Martin J. Slavinand assigned to the assignee herein. Said system proposes the use of acoder associated with each utilization control for transmitting data toa data line in assigned time slots representative of the state of saidutilization control, and a decoder associated with the correspondingutilization circuits for detecting in assigned time slots from said dataline said state data and controlling said utilization circuits inresponse thereto. The coders and decoders of said system are connectedin series for sequential operation. This system suffers from thedisadvantage that if the data line or series connection breaks, theelements downstream of the break are rendered inoperative. Further, theprovision of both series connections and a separate data line adds tothe cabling and expense of the system. An improvement on the system ofU.S. Pat. No. 3,566,038 is disclosed in U.S. Pat. No. 3,585,595, issuedon June I5, 1971, to Martin J. Slavin, Kenneth Cohen and Morton Pullman,and also assigned to the assignee herein. In the latter system, the dataline is eliminated. The respectively series-connected coders anddecoders are sequentially activated to a first active state, duringwhich they are operative to perform their assigned functions.Thereafter, each activated coder and decoder assumes an inactive statein which they permit the passage of control signals and datatherethrough.-A column timer is placed in series connection with thecoders and decoders for applying control signals thereto. One difficultywith this system is that if the column timer is disabled, then all ofthe decoders, coders and utilization circuits associated therewith arealso disabled. Further, neither of the two above-described systemsprovides means for detecting the status of automatically operableutilization devices, such as oxygen supply systems.

SUMMARY OF THE INVENTION tween the column timers through theseries-connected coders and decoders while said coders and decoders arein the inactive state. The two column timers are adapted to applycontrol signals to the coders and decoders during alternate cycles ofthe system. Supervisory utilization circuit means would be connected tothe respective column timer signal detector means for sounding an alarmshould a signal not be received from the other of the column timers.

Two or more series-connected groups of coders and decoders may beprovided connected between a single pair of column timers. Each group ofdecoders and coders would be alternately actuated by one of the columntimers, so that during each cycle, each column timer is activating aportion of the groups.

Means is also incorporated in each of the coders to detect the status ofa utilization circuit and to transmit a signal representative of saidstatus to the column timers.

Accordingly, it is an object of this invention to provide a controlsystem which permits individual control of a variety of utilizationcircuits.

Another object of the invention is to provide a control systemincorporating series-connected elements wherein elements on both sidesof a break in said closed loop are operative despite said break, andwherein the system will function despite a breakdown in the supervisoryarrangement due to the provision'of two such supervisory arrangementsconnected at opposed ends of the series-connected elements.

A further object of the invention is to provide a con- I trol systemincorporating means for determining the status of utilization circuits.

Still other objects and advantages of the invention will in part beobvious and will in part be apparent from the specification.

The invention accordingly comprises the features of construction,combinations of elements, and arrangement of parts which will beexemplified in the constructions hereinafter set forth, and the scope ofthe invention will be indicated in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic representationof a decoder of i the system of FIG. 1; and

FIG. 4 is a schematic representation of the means for detecting thestatus of a utilization circuit of the system of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The control system according tothe invention is an improvement in the control system disclosed in U.S.Pat. No. 3,585,595, and accordingly, the specification and drawings ofsaid patent are incorporated herein by reference. The reference numeralsof said patent are utilized to identify like elements in the controlsystem according to the invention. Reference is had to said patent for adetailed description of the structure and operation of the system, andthe components thereof to the extent that said system and componentscorrespond to the control system according to the invention.

Referring now to FIG. 1, the control system depicted incorporates amaster column timer 10 having three coder terminals, 12A, 12B and 12C,and three decoder terminals, 16A, 16B and 16C. Further, master columntimer 10' is provided with a pair of master/slave designation terminals,400 and 402, joined by an external lead 404. The system also includesslave column timer 10" having three coder terminals, 12A, 12B and 12C,and three decoder terminals, 16A, 16B and 16C. Slave column timer 10" isalso provided with a pair of master/slave designation terminals, 400'and 402. Slave columntimer 10" is identical to master column timer 10'except for the absence of external lead 404, which is utilized to modifymaster column timer 10 so that said column timer serves as a master inthe system of FIG. 1, as will be more particularly described below.

Master column timer l and slave column timer are positioned betweenthree groups of discrete stations, each of said group of stations havinga coder 20,

a decoder 34, utilization controls 30, and utilization circuits 32associated therewith. Group A of said stations consists of a pluralityof coders 20a, b, c, n connected in series between coder terminals 12Aand 12A of the two column timers. Each coder is provided with a pair ofterminals 22 and 24 for said series connection, interconnected by coderline 26. Operatively connected to each coder 20, by means of lines 28,are one or more utilization controls 28a, b, c, 11. Each utilizationcontrol is adapted to be set in one or more states associated with thestates in which the corresponding utilization circuits 32 a, b, c, n areto be placed. Each coder 20 is adapted to detect the states of itscorresponding utilization controls 30 and to store data representativeof said states.

A plurality of decoders 34a, b', c, n, are connected in series betweendecoder terminals 16A and 16A. Each decoder is provided with a pair ofterminals 36 and 38 interconnected in said series connection by decoderline 40. Each decoder 34 is connected by means of lines 42 to one or agroup of utilization circuits 32. Said decoders are adapted to placetheir corresponding utilization circuits in the desired state inresponse to data received thereby in assigned time slots. Further, eachdecoder is connected to its associated utilization circuits by a line406 through which the state of a utilization circuit may be detectedupon command and transmitted to the column timers.

Each coder 20 is associated with the decoder 34' connected to theutilization circuits 32 which are, in turn associated with itsutilization controls 30. Thus, coder 20b is associated with utilizationcontrols 30b which are adapted to control utilization circuits 32b.

Accordingly, decoder 34b is associated with coder 20b. The associatedcoders and decoders are disposed in their respective series connectionin the same sequence. In this manner, when, said coders and decoders'are sequentially operated, only the corresponding pair of said codersand decoders are activated at any instant. Groups of stations B and Care formed in a like manner of similar components.

The control system according to the invention is adapted for cyclicaloperation. During each cycle, one of master column timer l0 and slavecolumn timer 10" applies a control signal to either of coder terminals12A or 12A. Each cycle of said control signal is divided into at leastn+1 frames, each frame being in turn divided into a plurality of timeslots. Each of said time slots within the cycle is allotted to aparticular element of data to be transmitted during the operation of thesystem, while the frames would be allocated in sequence to eachassociated coder and decoder. Thus, the first time frame of a cyclemight be associated with coder 20a and decoder 34a, the second timeframe might be associated with coder 20b and decoder 34b, etc. Withinthe first time frame, time slots would be allocated to contain datarepresentative of the states of each of the three utilization controls30a. Similarly, in the third time frame, time slots would beallocated tocontain data representative of the states of the two utilizationcontrols 300. The control signal would include synchronization and clocktiming components in assigned time slots and'time frames. Thesynchronization component would be utilized to reset coders 2 0 anddecoders 34' either at the end or beginning of a cycle. The columntimers are also adapted to apply control signals of similar format toeither of decoder terminals 16a and 16a.

One time frame, preferably the last time frame would be allocated forcommunication between master column timer 10' and slave column timer10". Said column timers do not simultaneously apply the control signalsto the series connected coder and decoders. Rather, said column timersare adapted to alternately apply said control signals. Thus, during oneor more cycles, master column timer 10' might apply the control signalsto coder terminals 12A and 12C and decoder terminals 16A and 16C ofgroups A and C while slave column timer 10" simultaneously appliescontrol signals to coder terminal 128 anddecoder terminals 168' of groupB. During the next one or more cycles, slave column timer 10' appliescontrol signals to the coders and decoders of groups A and C whilemaster column timer 10 applies control signals to group B.

Y The column timers are designated master and slave since master columntimer [0 is adapted to transmit data identifying the groups to which itwill apply control signals during the next cycle, slave column timer l0"acting in response to said transmitted data to apply its control signalsto the other of said groups. Said data would be transmitted during thetime frame of each cycle allocated for column timer communication. Saidtime frame is preferably at the end of each cycle since, at that point,all of the coders and decoders are in the inactive state, as will bemore particularly described below. While the embodiment of the controlsystem depicted in the drawings incorporates three groups, any number ofgroups of discrete stations may be provided between the master and slavecolumn timers.

During normal operation, the master and slave column timers alternatelyapply control signals to each group so that control signals are appliedin one or the other direction to each of groups A, B and C during eachcycle. Should one of the master or slave column timers fail, that factwould be detected in the other of said master and slave column timersdue to the failure to detect a signal in the time frame allocated forcolumn timer communication. In this event, the remaining column timerwould alternately apply control signals to groups A and B and to group Cso that said control signals are applied to each group at least duringevery other cycle. The bit rate of the control signal is sufficientlyfast so that such alternate operation is sufficient for control of theutilization circuits 32. Thus, the system will remain operational evenin the face of the failure of one of the master or slave column timers.Further, the arrangement eliminates the necessity for the relativelylong return cable provided between the single column timer and coder nand decoder 34n of the system of US. Pat. No. 3,585,595. The latterconsideration is particularly important for applications where weight issignificant, as in the case of service systems for aircraft.

By way of example, one cycle of the control system according to theinvention wherein a control signal is applied by master column timer 10'to group A will be described. In said cycle, master column timer 10'applies said control signal to coder terminal 12A, all of said coders 20having been previously reset to a notyet-activated state in response tothe synchronization component during the previous cycle. The controlsignal would be detected at terminal 22 of coder 20a to place said coderin an active state which is maintained during the time frame assignedthereto consisting of a predetermined number of time slots. During saidtime frame, coder 20a transmits back through terminal 22 thereof, inappropriate time slots, the data representative of the state ofutilization controls 30a. At the end of said time period, as determinedby the detection of a predetermined number of said clock timingcomponents, coder 20a is placed in an inactive state during which thedata stored therein is no longer transmitted,

but the control signal is passed therethrough, out of ter-. minal 24 andinto terminal 22 of coder 20b. Coder 20b.

is then activated for the period of its associated time frame andtransmits the data representative of the state of utilization controls30b out of its terminal 22 in the direction of coder terminal 12A ofmaster column timer 10. Since coder 20a is in its inactive state, saiddata is passed therethrough from terminal 24 to terminal 20 and to coderterminal 12A. this sequential operation continues until the nth coderhas gone through an active state, at which time the column timercommunication signal is transmitted and a synchronization component ofthe control signal resets all of coders 20 to dispose said coders in thenot-yet-activated state for the next cycle. Each coder, when firstactivated, receives the control signal from the downstream coders andpasses the data back through said downstream coders to column timer 10.

In like manner, master column timer 10' applies a control signal todecoder terminal 16 which first activates decoder 34a. When soactivated, said decoder receives in assigned time slots, the datatransmitted by coder 20a, said column timer having interposed said datain the control signal applied from decoder terminal 16A. In response tosaid data, decoder 34a places I utilization circuits 32a in the desiredstate. Also during said time frame, if the control signal contains acommand in an assigned time slot to determine the status of autilization circuit, decoder 34a detects the status of one ofutilization circuits 32a and applies data representative of said statusto assigned time slots in the control signal. Unlike the coders,decoders 34 do not transmit this status data in the downstreamdirection, but rather, add said data to the control signal transmittedupstream to the next decoder in the sequence. After remaining active forthe time frame associated therewith, decoder 34a assumes an inactivestate and passes the control signal along decoder line 40 from itsterminal 38 to the terminal 36 of decoder 34b. In the embodiment of thecontrol system shown in the drawings, decoders 34' do not require thecapability of transmitting data back to the column timers, and need onlypass the control signal therethrough during their inactive andnot-yet-activated states.

All of decoders 20 are preferably identical and permitinterchangeability and ready maintenance. In like manner, all of thedecoders are preferably identical and interchangeable among themselves,the operation of the system being dependent on the placement of aparticular coder or decoder in the series connection, rather than thedesign of a particular one of said coders or decoders.

Group A would operate in the same manner if the control signal wereapplied to coder terminal 12A and decoder terminal 16A. In such a case,coder Min and decoder 34n' would be the first activated of said codersand decoders, the remaining coders and decoders being sequentiallyoperated in the manner described above with the data from the respectivecoders being transmitted back to slave column timer 10" for applicationto said decoders.

The system is provided with a supervisory control 44 connected to mastercolumn timer 10' through line 46. Said supervisory control is preferablycentrally located and adapted to apply data to column timer 10 duringappropriate time slots to govern the state of certain utilizationcircuits 32. The master column timer is adapted to apply the data fromsupervisory control 44,

if present, in place of the corresponding data from the appropriatecoders 20 so that the state of the utilization circuits is determined bythe state of supervisory control 44. The system also includes asupervisory utilization circuit 48 connected to master column timer 10'by line 50, said column timer being adapted to actuate said supervisoryutilization circuit upon detecting certain data in assigned time slotsof said control signal, and further, to activate said supervisoryutilization circuit to provide an alarm if the failure of slave columntimer 10 is detected. Similarly, a supervisory utilization circuit 48'is coupled by line 50' to slave column timer 10" for providing anindication of the failure of master column timer 10', as well asproviding indication of the status of certain of the utilizationcircuits. A supervisory utilization control could also be provided inconjunction with slave column timer l0". Supervisory utilizationcircuits 48 and 48 would detect the utilization circuit status datatransmitted by the decoders upon command to display the status of saidutilization circuits. The command directing the determination ofutilization circuit status would be initiated by supervisory utilizationcontrol 44.

In order to more particularly understand the operation of the system andfurther-embodiments and features thereof, reference is had to FIGS. 2 4of U.S. Pat. No. 3,585,595 and the description thereof in said patent.The detailed structure of the components of the control system accordingto the invention could be formed as described in said patent except asotherwise discussed below in connection with FIG. 2 hereof. Referringnow to FIG. 2 hereof, a schematic representation of the portion ofcolumn timer associated with groups A and B is depicted. Master columntimer 10 differs from column timer 10 of U.S. Pat. No. 3,585,595principally in the provision of circuitry associated with thecommunication between the master and slave column timers. Further,instead of controlling the direction of flow of control signals in theleft and right directions of a closed loop, as in the case of U.S. Pat.No. 3,585,595, counter 64 controls the alternate application of thecontrol signal to either group A or group B through signals appliedalong lines 78 and 80 respectively. Similarly, transmitters 80 and 92are connected to coder terminal 12A and decoder terminal 16Arespectively of group A, while transmitters 86 and 94 are connected tocoder terminal 12B and decoder terminal 168 respectively of group B.

A further difference is the substitution of error detector 408 for looperror detector 96. Error detector'408 is adapted to detect if one of thecoders or decoders in each group is shorted by detecting any discrepancybetween the clock signals received from the coder and decoder terminalof each group. If such a discrepancy is identified, then appropriatesignals are applied along lines 112 and 116 to coder clock/data logic 72and decoder clock/data logic 76 so that instructions for the resettingof utilization circuits 32 are transmitted only in the time framesassociated with the coders and decoders on the same side of said shortedcoder or decoder as master column timer 10. In other words, if coder 200of group A is shorted, that fact would be detected by the discrepancybetween the signals received at coder terminal 12A and decoder terminal16A when control signals are applied to group A by slave column timer10". In response to such a detection, a suitable alarm would be actuatedin supervisory utilization circuit 48 and only decoders 34a and 34bwould be operated by the signal from the master column timer 10'. Thecontrol signal from slave. column timer 10'', which is substantiallyidentical to the master slave column timer, would activate decoders3411', 34n-1, 34d, so that all but the shorted decoder would function inthe proper manner.

Communication between the master and slave column timers is achieved bymeans of master or slave circuit 410, column timer signal generator 412and column timer signal detector 414. Column timer signal detector 414is connected to each of coder terminals 12A and 12B and decoder terminal16A and 168 through receivers 100, 102, 96 and 98 respectively and lines416, 418, 420 and 422 respectively. Said column timer signal detectoroperates in response to timing signals received along line 424 frombasic timing decoding matrix 68. Certain data in assigned time slots inthe column timer signal received from slave column timer 10" is appliedalong line 426 to supervisory utilization circuit 48 for the display ofsaid data or the actuation of alarms. Further data in assigned timeslots of said column timer signal detector is applied along line 428 tomaster or slave circuit 410. This data would include the dataidentifying the last group to which slave column timer 10" applied theoperating signal. Master or slave circuit 410 is provided withmaster/slave designation terminals 400 and 402, and since said terminalsare joined by external lead 404, the column timer circuit of FIG. 2 isdesignated as the master. Were external lead 404 to be opened, thencolumn timer 10 would be designated as the slave. Since the column timerof FIG. 2 is designated as the master, master or slave circuit 410automatically transmits a signal along line 430 to counter 64 directingthe alternate application of output signals along lines 78 and of saidcounter for the alternate application of the control signal to groups Aand B in alternate successive periods, which periods may each consist ofa single cycle.

If the column timer of FIG. 2 were the slave column timer (external lead404 opened), then the signal applied along line 430 would depend on thesignal received from column timer signal detector 414. Thus, if thecolumn timer signal from the master column timer indicated that themaster column timer would drive group A in the next cycle, then masteror slave circuit 410 would direct counter 64 to drive group B in thenext cycle. Should no column timer signal be detected for apredetermined period of time, then master or slave circuit 410 would beadapted to automatically change the column timer operation to the mastermode wherein counter 64 is automatically alternately directed to applythe control signal to groups A and B.

Further, master or slave circuit 410 applies a signal along line 432 tocolumn timer signal generator 412 representative of the group to beactivated in the annexed cycle for incorporation in the column timersignal. Said column timer signal generator operates in response totiming signals received from basic timing decoding matrix 68 along line434. Further inputs may be provided to column timer signal generator 412for incorporation in the column timer signal as desired. Thus, forexample, certain utilization control or utilization circuit statusinformation could be detected at error detector 408 and applied tocolurnn timer signal generator 412 in assigned time slots, if desired.The column timer signal is applied along line 436 to decoder clock/datalogic 76 and coder clock/data logic 72 for application to the coderanddecoder terminals in the time frame assigned to column timercommunication.

The coders, decoders, utilization controls and utilization circuits moreparticularly described in U.S. Pat. No. 3,585,595 may be incorporated inthe system according to the invention. An alternate embodiment of saiddecoder and utilization circuits is depicted in FIGS. 3 and 4. The coder34' of FIG. 3 is sub-stantially identical to the coder of FIG. 4 of saidpatent except for the provision of line 406 intermediate utilizationcircuits 32 and data storage registers and drivers 294 for theapplication of a utilization circuit status signal to said data storageregisters and drivers, and line 438 interconnecting said data storageregisters and drivers and AND gates 316 and 320. The latter line permitsthe application of said utilization circuit status signal to appropriatetime slots in the frame of the control signal associated with thatparticular decoder. Determination of utilization circuit status isachieved in response to one or more data bits in assigned time slots insaid frame received by the data storage registers and drivers anddirectingthe performance of the utilization circuit statusdetermination. The utilization circuit status data could be detected byerror detector 408 of the column timer of FIG. 2 for application tosupervisory utilization circuit 48 along line 104.

Referring now to FIG. 4, one example of a utilization circuitparticularly adapted for status determination is depicted. In saidarrangement, the status of actuator 440 is to be detected. The commandfor status determination is received from decoder 34' along line 42'which results in the application of a voltage of a predetermined valueto actuator 440. An output voltage is produced along lines 442 fromactuator 440 and applied to comparators 444 and 446. In one embodiment,said comparators would be adapted to determine if the output signalalong line 442 lies within a predetermined voltage range, comparator 444determining the upper limit of the range and comparator 446 determiningthe lower limit of the range. If the voltage on line 442 lies outside ofthe predetermined range, a signal would be applied from one ofcomparators 444 and 446 to OR gate 448 along lines 450 and 452respectively. The output of OR gate 448 is applied along line 451 totransmitter 453, which applies an actuator status signal along line 406to decoder 34. An additional feature of the circuit of FIG. 4 is thatthe signal from OR gate 448 is also applied to OR gate 454, the outputof which is connected along line 456 to lamp 458 located at the discretestation associated with actuator 440 to provide an immediate visualindication of the failure of actuator 440 to pass the applied test. Lamp458 may constitute one of the utilization circuits controlled byutilization controls 30, in which case the other input to OR gate 454would be line 42" coupled to decoder 34' for the application of controlsignals to the lamp in response to the status of said utilizationcontrols.

In one application of the control system according to the invention tothe service system of aircraft, actuator 440 may be associated withsafety equipment located at each discrete station, such as oxygenequipment. Other components of such safety equipment could also betested, such as the solenoid controls thereof.

It will thus be seen that the objects set forth above, and those madeapparant from the preceding description, are efficiently attainedand,.since certain changes may be made in the above constructionswithout departing from the spirit and scope of the invention, it isintended that allmatter contained in the above description or shown inthe accompanying drawings shall be interpreted as illustrative and notin a limiting sense.

It is also to be understood that the following claims are intended tocover all of the generic and specific features of the invention hereindescribed, and all statements of the scope of the invention which, as amatter of language, might be said to fall therebetween.

What is claimed is:

l. A control system for a plurality of discrete stations comprising aplurality of utilization circuits; at least one utilization controlmeans disposed at each of said stations and associated with at least oneof said utilization circuits; a plurality of series connected codermeans for detecting the state of the utilization control meansassociated therewith; decoder means associated with each of said codermeans for controlling the state of the corresponding utilizationcircuits, said decoder means being in series connection in the samesequence as said corresponding coder means; and first and second columntimer means, said series connected coder and decoder means beingconnected between said first and second column timer means, said firstand second column timer means being adapted to alternately apply controlsignals to said series connections, said coder and decoder means beingsequentially activated in response to said control signals duringassigned time frames, each of said coder means being adapted, when firstactivated during a cycle of said system, to transmit in assigned timeslots within its time frame data representative of the state of theutilization control means associated therewith to the column timer meansapplying said control signal through any of said coder means previouslyactivated during said cycle, said coder means being adapted tothereafter for the balance of said cycle to pass the control signal andthe data transmitted by downstream coder means, said first and secondcolumn timer means being adapted to incorporate in the control signalrespectively applied to said decoder means the data representative ofsaid utilization control means states transmitted thereto by said codermeans, each of said decoder means being adapted, when first activatedduring a cycle of said system, to receive during assigned time slotssaid data from said column timer means through any previously activateddecoder means to control the corresponding utilization circuits, saiddecoder means being adapted to thereafter for the balance of said cyclepassed the control signal to downstream decoders, whereby each of saidutilization circuits is placed in a state responsive to the state of itscorresponding utilization control means.

2. A control system as recited in claim 1, incorporating at least twogroups of said series connectedcoder and decoder means and associatedutilization circuits and utilization control means connected betweensaid first and second column timer means, each of said first and secondcolumn timer means alternately applying said control signal to first andsecond portions of said groups of coder and decoder means duringsuccessive time periods so that, during normal operation, all of saidgroups of coder and decoder means have a control signal applied theretoduring each of said successive periods by one of said first and secondcolumn timer means.

3. A control system as recited .in claim 2, wherein each of said firstand second column timer means includes column timer signal generatormeans for producing in a predetermined time frame of each cycle a columntimer signal, and column timer signal detector means for detecting saidcolumn timer signal in said time frame.

4. A control system as recited in claim 3, wherein said first columntimer means includes-means for automatically alternately applying saidcontrol signal to the two portions of said groups of coder and decodermeans in successive time periods, said second column timer meansapplying its control signal to the groups of coders and decodersdesignated in the column timer signal from said first column timermeans.

5. A control system as recited in claim 4, wherein said second columntimer means automatically alternately applies said control signal tosaid first and second portions of said groups of coder and decoder meansupon failure to receive a column timer signal from said first columntimer means for a predetermined period.

6. A control system as recited in claim 4, wherein each of said firstand second column timer means is adapted to alternately apply saidcontrol signal to said groups of coder and decoder means upon thefailure of the other of said first and second column timer means.

7. A control system as recited in claim 3, including supervisoryutilization circuit means connected to each of said first and secondcolumn timer means for actuation to provide an indication should thecolumn timer signal detector means of either of said first or secondcolumn timer means fail to detect the column timer signal from the otherof said first or second column timer means. i

8. A control system as recited in claim 1, including a furtherutilization circuit associated with at least a portion of said decodermeans, said decoder means including means for detecting the status ofthe further utilization circuit associated therewith in response to acommand signal in the time frame of the control signal associatedtherewith, and for applying a status signal to predetermined time slotsin the time frame associated therewith for transmittal upstream alongthe series connected decoder means to one of the first and second columntimer means which did not apply said control signal, said one of saidfirst and second column timer means including means for detecting saidstatus signal period.

9. A control system as recited in claim 8, wherein said status detectormeans further includes means for actuating one of said first-mentionedutilization circuits associated therewith in response to the detectionof a predetermined state of said further utilization circuit to placesaid first-mentioned utilization circuit in a predetermined identifiablestate.

10. A control system as recited in claim 9, wherein said control systemis a passenger aircraft service system including an oxygen supplysystem, said further utilization circuit being control means for saidoxygen supply system.

11. A control system as recited in claim 1, wherein said first andsecond column timer means are each adapted to produce control signalsincorporating a synchronization portion in each cycle of said system,said coder and decoder means being adapted to be reset in responsetosaid synchronization portion to commence a new cycle of said system.

12. A control system as recited in claim 1, wherein each of said'firstand second column timer means includes error detector means to receivethe control signals transmitted through said coder and decoder meansfrom the other of said column timer means to detect discrepancies in thesignals sotransmitted to detect defective code and decoder means; andmeans for controlling the generation of said control signals in saidfirst and second column timer means in response to said error detectormeans to prevent the application of operative data to said controlsignal time frames associated with the defective coder or decoder meansand the coder or decoder means downstream of said defective coder ordecoder means.

13. A control system as recited in claim 1, wherein each of said firstand second column timer means is adapted to produce control signalsincluding clock timing components in assigned time slots, the sequentialoperation of said system being responsive to said clock timingcomponents. 7

14. A control system as recited in claim 1, wherein said coder means aresubstantially identical, and said decoder means are substantiallyidentical.

15. A control system as recited in claim 1, including supervisoryutilization control means connected to'at least one of said first andsecond column timer means and associated with at least one of saidutilization circuits, said one column timer means being adapted todetect the state of said supervisory utilization control means and toincorporate in the time slots of the control signal applied to saiddecoder means data representative of said supervisory utilizationcontrol means states for the control of said utilization circuits by thecorresponding decoder means, said data being applied in place of thedata transmitted by the coder means as sociated with said utilizationcircuits.

16. A control system as recited in claim 1, wherein said coder means areadapted to establish the state of at least one utilization control meansassociated therewith, said system including supervisory utilizationcontrol means associated with said controllable utilization controlmeans, said column timer means being adapted to detect the state of saidsupervisory utilization control means and to incorporate in assignedtime slots of the control signal applied to said series connected codermeans data representative of the state of said supervisory utilizationcontrol means, each of said coder means being adapted to receive suchdata when first activated for controlling the state of said controllableutilization control means.

17. A control system as recited in claim 1, wherein each of said firstand second column timer means is adapted to produce a control signal forapplication to said series connected coder means includingsynchronization and clock timing components, the sequen-tial operationof said coder means between a first not-yetactivated state, a secondactive state and a third inactive state being in response to said clocktiming components during each cycle of said system, said coder meansbeing adapted to be reset to said not-yetactivated state in response tosaid synchronization component.

18. A control system as recited in claim 17, wherein said coder meansincludes a pair of terminals for said series connection; direction logicmeans connected to saidterminals for producing a direction signalrepresentative of the terminal from which said control signal isreceived; data storage means for storing data representative of thestate of the corresponding utilization control means; gate signal meansfor generating, in response to said clock timing components of saidcontrol signal applied thereto during said active and inactive states ofsaid coder means, gating signals representative respectively of saidinactive state, active state, and the time slots assigned to thetransmission of data; and gating means responsive to said gating anddirection signals, said gatingmeans being connected to the terminal atwhich said control signal is received to apply to said terminal, duringsaid active state, the data stored in said data storage means and,during the time slots assigned to the transmission of data occurringduring said inactive state, the data received from the other of saidterminals, said gating means being connected to the other of saidterminals, for the application thereto, during said inactive state, ofthe clock timing components of said control signal.

19. A control system as recited in claim 18, wherein said control signalincludes data transmitted by said column timer means in assigned timeslots, said data storage means being connected to said terminals toreceive such data during assigned time frames, said gating signal meansproducing gating signals representative of the time slots assigned tosaid data transmitted by said column timer, said gating means, duringsaid time slots assigned to said column timer data occurring during saidinactive state, applying said column timer data to said other terminal.

20. A control system as recited in claim 19, wherein said decoder meansincludes a pair of terminals for said series connection; direction logicmeans connected to said terminals for producing a direction signalrepresentative of the terminal to which said control signal is

1. A control system for a plurality of discrete stations comprising a plurality of utilization circuits; at least one utilization control means disposed at each of said stations and associated with at least one of said utilization circuits; a plurality of series connected coder means for detecting the state of the utilization control means associated therewith; decoder means associated with each of said coder means for controlling the state of the corresponding utilization circuits, said decoder means being in series connection in the same sequence as said corresponding coder means; and first and second column timer means, said series connected coder and decoder means being connected between said first and second column timer means, said first and second column timer means being adapted to alternately apply control signals to said series connections, said coder and decoder means being sequentially activated in response to said control signals during assigned time frames, each of said coder means being adapted, when first activated during a cycle of said system, to transmit in assigned time slots within its time frame data representative of the state of the utilization control means associated therewith to the column timer means applying said control signal through any of said coder means previously activated during said cycle, said coder means being adapted to thereafter for the balance of said cycle to pass the control signal and the data transmitted by downstream coder means, said first and second column timer means being adapted to incorporate in the control signal respectively applied to said decoder means the data representative of said utilization control means states transmitted thereto by said coder means, each of said decoder means being adapted, when first activated during a cycle of said system, to receive during assigned time slots said data from said column timer means through any previously activated decoder means to control the corresponding utilization circuits, said decoder means being adapted to thereafter for the balance of said cycle passed the control signal to downstream decoders, whereby each of said utilization circuits is placed in a state responsive to the state of its corresponding utilization control means.
 2. A control system as recited in claim 1, incorporating at least two groups of said series connected coder and decoder means and associated utilization circuits and utilization control means connected between said first and second column timer means, each of said first and second column timer means alternately applying said control signal to first and second portions of said groups of coder and decoder means during successive time periods so that, during normal operation, all of said groups of coder and decoder means have a control signal applied thereto during each of said successive periods by one of said first and second column timer means.
 3. A control system as recited in claim 2, wherein each of said first and sEcond column timer means includes column timer signal generator means for producing in a predetermined time frame of each cycle a column timer signal, and column timer signal detector means for detecting said column timer signal in said time frame.
 4. A control system as recited in claim 3, wherein said first column timer means includes means for automatically alternately applying said control signal to the two portions of said groups of coder and decoder means in successive time periods, said second column timer means applying its control signal to the groups of coders and decoders designated in the column timer signal from said first column timer means.
 5. A control system as recited in claim 4, wherein said second column timer means automatically alternately applies said control signal to said first and second portions of said groups of coder and decoder means upon failure to receive a column timer signal from said first column timer means for a predetermined period.
 6. A control system as recited in claim 4, wherein each of said first and second column timer means is adapted to alternately apply said control signal to said groups of coder and decoder means upon the failure of the other of said first and second column timer means.
 7. A control system as recited in claim 3, including supervisory utilization circuit means connected to each of said first and second column timer means for actuation to provide an indication should the column timer signal detector means of either of said first or second column timer means fail to detect the column timer signal from the other of said first or second column timer means.
 8. A control system as recited in claim 1, including a further utilization circuit associated with at least a portion of said decoder means, said decoder means including means for detecting the status of the further utilization circuit associated therewith in response to a command signal in the time frame of the control signal associated therewith, and for applying a status signal to predetermined time slots in the time frame associated therewith for transmittal upstream along the series connected decoder means to one of the first and second column timer means which did not apply said control signal, said one of said first and second column timer means including means for detecting said status signal period.
 9. A control system as recited in claim 8, wherein said status detector means further includes means for actuating one of said first-mentioned utilization circuits associated therewith in response to the detection of a predetermined state of said further utilization circuit to place said first-mentioned utilization circuit in a predetermined identifiable state.
 10. A control system as recited in claim 9, wherein said control system is a passenger aircraft service system including an oxygen supply system, said further utilization circuit being control means for said oxygen supply system.
 11. A control system as recited in claim 1, wherein said first and second column timer means are each adapted to produce control signals incorporating a synchronization portion in each cycle of said system, said coder and decoder means being adapted to be reset in response to said synchronization portion to commence a new cycle of said system.
 12. A control system as recited in claim 1, wherein each of said first and second column timer means includes error detector means to receive the control signals transmitted through said coder and decoder means from the other of said column timer means to detect discrepancies in the signals so transmitted to detect defective code and decoder means; and means for controlling the generation of said control signals in said first and second column timer means in response to said error detector means to prevent the application of operative data to said control signal time frames associated with the defective coder or decoder means and the coder or decoder means downstream of said defective coder or decoder means.
 13. A cOntrol system as recited in claim 1, wherein each of said first and second column timer means is adapted to produce control signals including clock timing components in assigned time slots, the sequential operation of said system being responsive to said clock timing components.
 14. A control system as recited in claim 1, wherein said coder means are substantially identical, and said decoder means are substantially identical.
 15. A control system as recited in claim 1, including supervisory utilization control means connected to at least one of said first and second column timer means and associated with at least one of said utilization circuits, said one column timer means being adapted to detect the state of said supervisory utilization control means and to incorporate in the time slots of the control signal applied to said decoder means data representative of said supervisory utilization control means states for the control of said utilization circuits by the corresponding decoder means, said data being applied in place of the data transmitted by the coder means associated with said utilization circuits.
 16. A control system as recited in claim 1, wherein said coder means are adapted to establish the state of at least one utilization control means associated therewith, said system including supervisory utilization control means associated with said controllable utilization control means, said column timer means being adapted to detect the state of said supervisory utilization control means and to incorporate in assigned time slots of the control signal applied to said series connected coder means data representative of the state of said supervisory utilization control means, each of said coder means being adapted to receive such data when first activated for controlling the state of said controllable utilization control means.
 17. A control system as recited in claim 1, wherein each of said first and second column timer means is adapted to produce a control signal for application to said series connected coder means including synchronization and clock timing components, the sequen-tial operation of said coder means between a first not-yet-activated state, a second active state and a third inactive state being in response to said clock timing components during each cycle of said system, said coder means being adapted to be reset to said not-yet-activated state in response to said synchronization component.
 18. A control system as recited in claim 17, wherein said coder means includes a pair of terminals for said series connection; direction logic means connected to said terminals for producing a direction signal representative of the terminal from which said control signal is received; data storage means for storing data representative of the state of the corresponding utilization control means; gate signal means for generating, in response to said clock timing components of said control signal applied thereto during said active and inactive states of said coder means, gating signals representative respectively of said inactive state, active state, and the time slots assigned to the transmission of data; and gating means responsive to said gating and direction signals, said gating means being connected to the terminal at which said control signal is received to apply to said terminal, during said active state, the data stored in said data storage means and, during the time slots assigned to the transmission of data occurring during said inactive state, the data received from the other of said terminals, said gating means being connected to the other of said terminals, for the application thereto, during said inactive state, of the clock timing components of said control signal.
 19. A control system as recited in claim 18, wherein said control signal includes data transmitted by said column timer means in assigned time slots, said data storage means being connected to said terminals to receive such data during assigned time frames, said gating signal means producing gating signals representative of the time slots assigned to said data transmitted by said column timer, said gating means, during said time slots assigned to said column timer data occurring during said inactive state, applying said column timer data to said other terminal.
 20. A control system as recited in claim 19, wherein said decoder means includes a pair of terminals for said series connection; direction logic means connected to said terminals for producing a direction signal representative of the terminal to which said control signal is applied; data storage means connected to said terminals for detecting data components of said control signal during assigned time slots; gating signal means for producing gating signals representative of said active and inactive states respectively in response to the clock timing components of said control signal and gating means responsive to said direction and gating signals for applying, during said inactive state, said control signal to the terminal to which said control signal was not applied. 